Design Space of Flexible Multigigabit LDPC Decoders. (30th May 2012)

• Record Type: Journal Article
• Authors: Schläfer, Philipp; Weis, Christian; Wehn, Norbert; Alles, Matthias
• Other Names: Masera Guido Academic Editor.
• Is Part Of: VLSI design. Volume 2012(2012)
• Publication Date: 2012-05-30
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2012/942893
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput while supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design space for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware is investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design space. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of column- versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The evolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art decoders.