A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems. (17th July 2012)
- Record Type:
- Journal Article
- Title:
- A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems. (17th July 2012)
- Main Title:
- A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
- Authors:
- Diamantopoulos, Dionysios
Siozios, Kostas
Xydis, Sotiris
Soudris, Dimitrios - Other Names:
- Reisis Dionysios Academic Editor.
- Abstract:
- Abstract : Shrinking silicon technologies, increasing logic densities and clock frequencies, lead to a rapid elevation in power density. Increased power density results in higher onchip temperature, which creates numerous problems tightly firmed to reliability degradation. Since typical low-power design has been proved inefficient to tackle the temperature increment by itself, device architects are facing the challenge of developing new methodologies to guarantee timing, power, and thermal integrity of the chip. In this paper, we propose a thermal-aware exploration framework targeting temperature hotspots elimination through the efficient exploration of multiple microarchitecture selections over the temperature-area trade-off curve. By carefully planning at design time the resources of the initial microarchitecture that should be replicated, the proposed methodology optimizes the system's thermal profile and attens on-chip temperature under various design constraints. The introduced framework does not impose any architectural or compiler modification, whereas it is orthogonal to any other thermal-aware methodology. For evaluation purposes, we employ the software-defined radio executed onto a thermal-aware instance of LEON3 processor. Based on experimental results, we found that our methodology leads to an architecture that exhibits temperature reduction of 17 Kelvin degrees, which leads to improvement against aging phenomena about 14%, with a controllable overhead in siliconAbstract : Shrinking silicon technologies, increasing logic densities and clock frequencies, lead to a rapid elevation in power density. Increased power density results in higher onchip temperature, which creates numerous problems tightly firmed to reliability degradation. Since typical low-power design has been proved inefficient to tackle the temperature increment by itself, device architects are facing the challenge of developing new methodologies to guarantee timing, power, and thermal integrity of the chip. In this paper, we propose a thermal-aware exploration framework targeting temperature hotspots elimination through the efficient exploration of multiple microarchitecture selections over the temperature-area trade-off curve. By carefully planning at design time the resources of the initial microarchitecture that should be replicated, the proposed methodology optimizes the system's thermal profile and attens on-chip temperature under various design constraints. The introduced framework does not impose any architectural or compiler modification, whereas it is orthogonal to any other thermal-aware methodology. For evaluation purposes, we employ the software-defined radio executed onto a thermal-aware instance of LEON3 processor. Based on experimental results, we found that our methodology leads to an architecture that exhibits temperature reduction of 17 Kelvin degrees, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, compared to the initial LEON3 instance. … (more)
- Is Part Of:
- VLSI design. Volume 2012(2012)
- Journal:
- VLSI design
- Issue:
- Volume 2012(2012)
- Issue Display:
- Volume 2012, Issue 2012 (2012)
- Year:
- 2012
- Volume:
- 2012
- Issue:
- 2012
- Issue Sort Value:
- 2012-2012-2012-0000
- Page Start:
- Page End:
- Publication Date:
- 2012-07-17
- Subjects:
- Integrated circuits -- Very large scale integration -- Periodicals
621.395 - Journal URLs:
- https://www.hindawi.com/journals/vlsi/ ↗
- DOI:
- 10.1155/2012/784945 ↗
- Languages:
- English
- ISSNs:
- 1065-514X
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD Digital store
- Ingest File:
- 17026.xml