Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications. (26th May 2011)

• Record Type: Journal Article
• Authors: Dhar, Subhra; Pattanaik, Manisha; Rajaram, Poolla
• Other Names: Strollo A. G. M. Academic Editor.
• Is Part Of: VLSI design. Volume 2011(2011)
• Publication Date: 2011-05-26
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2011/178516
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.