A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process. (December 2017)

• Record Type: Journal Article
• Authors: Wang, Jiafeng; Fan, Xiangning; Shi, Xiaoyang; Wang, Zhigong
• Is Part Of: Journal of semiconductors. Volume 38:Number 12(2017:Dec.)
• Publication Date: 2017-12
• Subjects: multi-standard -- frequency synthesizer -- fractional-N frequency divider -- phase switching -- Δ–Σ modulator; 2570; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/38/12/125001
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional- N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source-coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. Δ–Σ modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18 μ m CMOS process, the fractional- N frequency divider occupies a chip area of 1130 × 510 μ m 2 and it can correctly divide within the frequency range of 0.8–9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.