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APA Citation
Araujo, T., Cardoso, M. B., Nepomuceno, E. G., Llanos, C. H., & Arias-Garcia, J. (2021). a new floating-point adder FPGA-based implementation using RN-coding of numbers. Computers & electrical engineering, 90, . http://access.bl.uk/ark:/81055/vdc_100129509303.0x00004e