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HARVARD Citation
Araujo, T. et al. (2021). A new floating-point adder FPGA-based implementation using RN-coding of numbers. Computers & electrical engineering. p. . [Online].
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Araujo, T. et al. (2021). A new floating-point adder FPGA-based implementation using RN-coding of numbers. Computers & electrical engineering. p. . [Online].