Pipelined extended‐counting IΔΣ for 3D‐stacked CMOS image sensors. Issue 23 (25th September 2020)

• Record Type: Journal Article
• Authors: Callens, N.; Lefebvre, J.; Gielen, G.
• Is Part Of: Electronics letters. Volume 56:Issue 23(2020)
• Page Start: 1239
• Page End: 1241
• Publication Date: 2020-09-25
• Subjects: analogue‐digital conversion -- CMOS image sensors -- three‐dimensional integrated circuits; chopped images -- 3D‐stacked CMOS image sensors -- pipelined ADC -- high frame rate -- 3D‐stacked imagers -- novel multistage pipelined extended‐counting IΔΣ -- EC principle -- discontinuous rolling shutter artefacts -- temperature 8.0 K -- I; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2020.2030
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel multi‐stage pipelined extended‐counting (EC) I Δ Σ for 3D‐stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first‐order I Δ Σ ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D‐stacked imagers. By assigning each stage of the pipeline to a sub‐column of pixels while choosing another input stage of the pipeline when a sub‐column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.