Pipelined extended‐counting IΔΣ for 3D‐stacked CMOS image sensors. Issue 23 (25th September 2020) - Callens, N.; Lefebvre, J.; Gielen, G.
Abstract : A novel multi‐stage pipelined extended‐counting (EC) I Δ Σ for 3D‐stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first‐order I Δ Σ ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D‐stacked imagers. By assigning each stage of the pipeline to a sub‐column of pixels while choosing another input stage of the pipeline when a sub‐column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.