Timing error detection and correction for power efficiency: an aggressive scaling approach. Issue 6 (25th October 2018)

• Record Type: Journal Article
• Authors: Rathnala, Prasanthi; Wilmshurst, Tim; Kharaz, Ahmad
• Is Part Of: IET circuits, devices & systems. Volume 12:Issue 6(2018)
• Page Start: 707
• Page End: 712
• Publication Date: 2018-10-25
• Subjects: error correction -- error detection -- power consumption -- flip-flops -- clocks -- field programmable gate arrays -- low-power electronics; power efficiency -- aggressive scaling approach -- low-power consumption -- system level -- dynamic power -- supply voltage -- aggressive voltage scaling -- minimum power consumption -- aggressive frequency boosting -- time-borrowing feature -- system timing error tolerant -- error correction timing penalty -- power savings -- systems design -- processors -- error detection timing -- frequency varying hardware circuit -- flip-flop -- latch combination -- timing violation detection -- phase delaying -- field programmable gate array -- two-stage arithmetic pipeline; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5143
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Low‐power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low‐power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time‐borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip‐flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two‐stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.