Gate diffusion input based 4‐bit Vedic multiplier design. Issue 6 (15th May 2018)

• Record Type: Journal Article
• Authors: Garg, Ankit; Joshi, Garima
• Is Part Of: IET circuits, devices & systems. Volume 12:Issue 6(2018)
• Page Start: 764
• Page End: 770
• Publication Date: 2018-05-15
• Subjects: field programmable gate arrays -- multiplying circuits -- CMOS logic circuits -- logic design -- integrated circuit design -- MOSFET; gate diffusion input technique -- Vedic multiplier design -- Vedic multiplication -- field programmable gate array implementation -- circuit delay -- complementary metal oxide semiconductor logic circuit -- CMOS logic circuit -- Vedic mathematics -- GDI technique -- transistor count minimization -- TC minimization -- power dissipation -- supply voltage scaling -- bulk metal oxide semiconductor field effect transistor predictive technology -- model-based device parameter -- word length 4 bit -- size 130 nm; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2017.0454
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time‐consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)‐based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic‐based 4‐bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2‐bit Vedic multiplier using CMOS and GDI is compared. For the 4‐bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model‐based device parameters.