Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation. Issue 4 (30th April 2020)

• Record Type: Journal Article
• Authors: Chenouf, Amel; Djezzar, Boualem; Bentarzi, Hamid; Benabdelmoumene, Abdelmadjid
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 4(2020)
• Page Start: 555
• Page End: 561
• Publication Date: 2020-04-30
• Subjects: SRAM chips -- CMOS memory circuits -- negative bias temperature instability -- integrated circuit reliability -- MOSFET circuits; CMOS 6T-SRAM cell -- NBTI ageing mitigation -- CMOS 6T-static random access memory cells -- transistor sizing technique -- nMOS access transistors -- cell stability -- negative bias temperature instability mitigation -- pMOS pull-up transistors -- read stability -- write-ability; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0307
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T‐static random access memory (6T‐SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull‐up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T‐SRAM cell could be properly sized for improved read stability and write‐ability.