Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation. Issue 4 (30th April 2020) - Chenouf, Amel; Djezzar, Boualem; Bentarzi, Hamid; Benabdelmoumene, Abdelmadjid
Abstract : This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T‐static random access memory (6T‐SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull‐up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T‐SRAM cell could be properly sized for improved read stability and write‐ability.