Optimization of deep well gate-controlled dual direction SCR device for ESD protection in 0.5 μm CMOS process. (November 2019)
- Record Type:
- Journal Article
- Title:
- Optimization of deep well gate-controlled dual direction SCR device for ESD protection in 0.5 μm CMOS process. (November 2019)
- Main Title:
- Optimization of deep well gate-controlled dual direction SCR device for ESD protection in 0.5 μm CMOS process
- Authors:
- Wang, Yang
Jin, Xiangliang
Cao, Shengguo
Peng, Yan
Luo, Jun
Yang, Jun - Abstract:
- Highlights: DGC-DDSCR uses electric field effect to improve ESD characteristics. Study the effect of device size on ESD characteristics. The TCAD simulation results verify the basic principle of the device. Comparison on characteristics of the TDDSCR device and the DGC-DDSCR devices. Fabricated the TDDSCR device and the DGC-DDSCR device in 0.5 µm CMOS process. Abstract: Both traditional dual direction SCR (TDDSCR) and deep well gate-controlled dual direction SCR (DGC-DDSCR) are designed and fabricated in a 0.5 μm CMOS process. The ESD performance of the DDSCR device is predicted and verified by two-dimensional device simulation and transmission line pulse test results. The results show that when the TDDSCR changes the distance between the electrode N+ and the trigger surface P+(D4), the holding voltage increased from 10.1 V to 13.53 V, and the failure current remains stable (13.9A). The RS485 bus requires that the trigger voltage and the holding voltage of the ESD device be greater than 14.4 V, while TDDSCR is still unable to meet the on-chip ESD protection requirements for RS485 bus. However, when DGC-DDSCR increases the gate length (D4) of the anode and cathode, the holding voltage increases from 10.21 V to 15.18 V, and the failure current remains 14.63A. The test data has met the on-chip ESD protection requirements of the RS485 bus, and the size optimization problem of the DGC-DDSCR is discussed. The device has a strong current handling capability (91.25 mA/μm).
- Is Part Of:
- Solid-state electronics. Volume 161(2019)
- Journal:
- Solid-state electronics
- Issue:
- Volume 161(2019)
- Issue Display:
- Volume 161, Issue 2019 (2019)
- Year:
- 2019
- Volume:
- 161
- Issue:
- 2019
- Issue Sort Value:
- 2019-0161-2019-0000
- Page Start:
- Page End:
- Publication Date:
- 2019-11
- Subjects:
- DDSCR -- Gate-controlled -- High holding voltage -- Device simulation
Semiconductors -- Periodicals
Semiconducteurs -- Périodiques
621.38152 - Journal URLs:
- http://www.sciencedirect.com/science/journal/00381101 ↗
http://www.elsevier.com/journals ↗ - DOI:
- 10.1016/j.sse.2019.107634 ↗
- Languages:
- English
- ISSNs:
- 0038-1101
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 8327.385000
British Library DSC - BLDSS-3PM
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- 16442.xml