Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process. Issue 12 (1st June 2014)

• Record Type: Journal Article
• Authors: Kim, T.W.; Choi, B.D.; Kim, D.K.
• Is Part Of: Electronics letters. Volume 50:Issue 12(2014)
• Page Start: 876
• Page End: 877
• Publication Date: 2014-06-01
• Subjects: integrated circuit design -- integrated circuit interconnections -- CMOS integrated circuits -- error statistics -- probability; ID generation circuit -- via formation probability -- bit error rate -- CMOS process -- physical unclonable function -- via hole size -- design rule -- supply voltage variations -- time invariance -- size 0.18 mum; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.3474
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post‐processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.