0.012 mm2 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 psrms integrated jitter in 28 nm FD‐SOI. Issue 18 (1st September 2016)

• Record Type: Journal Article
• Authors: Gupta, N.; Lahiri, A.; Kumar, A.
• Is Part Of: Electronics letters. Volume 52:Issue 18(2016)
• Page Start: 1518
• Page End: 1520
• Publication Date: 2016-09-01
• Subjects: phase locked loops -- jitter -- protocols -- low‐power electronics -- system‐on‐chip -- voltage‐controlled oscillators -- charge pump circuits -- UHF filters -- UHF integrated circuits -- thermal noise -- silicon‐on‐insulator; FD‐SOI process -- multiprotocol PLL -- wireline standards -- HDMI1.4 -- USB2.0 -- DDR4 -- DisplayPort1.2 -- host clock generation -- low‐power system‐on‐chips -- automatic VCO gain -- charge‐pump current calibration circuits -- robust jitter performance -- loop‐filter capacitor -- dual‐path loop‐filter technique -- output jitter reduction -- loop‐filter resistor -- thermal noise -- power 800 muW -- frequency 0.1 GHz to 6.4 GHz -- time 14 ps -- size 28 nm -- frequency 21.25 MHz; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2016.0819
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A multi‐protocol PLL suitable for different wireline standards namely HDMI1.4, USB2.0, DDR4, DisplayPort1.2 and for host clock generation for low‐power system‐on‐chips is presented. The PLL employs automatic VCO gain and charge‐pump current calibration circuits to provide a near constant PLL bandwidth which enables a robust jitter performance across process, voltage, temperature. Without increasing the loop‐filter capacitor, dual‐path loop‐filter technique is employed to reduce output jitter due to thermal noise of loop‐filter resistor. The PLL designed in 28 nm fully depleted silicon on insulator (FD‐SOI) process has an output frequency range from 0.1 to 6.4 GHz, total rms integrated jitter of 14 ps at 21.25 MHz reference frequency, consumes 800 µW at 3.4 GHz VCO frequency and occupies an area of 0.012 mm 2 .