Advanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process. Issue 8 (1st April 2018)

• Record Type: Journal Article
• Authors: Meng, F.; Li, K.; Thomson, D.J.; Wilson, P.; Reed, G.T.
• Is Part Of: Electronics letters. Volume 54:Issue 8(2018)
• Page Start: 486
• Page End: 488
• Publication Date: 2018-04-01
• Subjects: high‐k dielectric thin films -- CMOS analogue integrated circuits -- integrated circuit layout -- high‐speed integrated circuits -- oscillators -- circuit optimisation -- transistor circuits; advanced layout techniques -- high‐speed analogue circuits -- HKMG CMOS process -- transistor finger optimization effect -- deep sub‐micron processes -- high‐K‐metal gate CMOS technology process -- oscillator -- figure of merit -- benchmark design -- size 28 nm -- size 440 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.4453
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : The effect of optimising the transistor finger width on the performance of high‐speed analogue circuits in deep sub‐micron processes is investigated, demonstrated in a 28 nm high‐K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.