Advanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process. Issue 8 (1st April 2018) - Meng, F.; Li, K.; Thomson, D.J.; Wilson, P.; Reed, G.T.
Abstract : The effect of optimising the transistor finger width on the performance of high‐speed analogue circuits in deep sub‐micron processes is investigated, demonstrated in a 28 nm high‐K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.