8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction. Issue 20 (1st October 2018)

• Record Type: Journal Article
• Authors: Yu, C.; Lee, D.; Park, H.; Jin, S.; Ahn, G.‐C.; Burm, J.
• Is Part Of: Electronics letters. Volume 54:Issue 20(2018)
• Page Start: 1156
• Page End: 1158
• Publication Date: 2018-10-01
• Subjects: clock and data recovery circuits -- frequency locked loops -- circuit tuning -- clocks -- CMOS digital integrated circuits; full synthesised continuous‐half‐rate reference‐less all‐digital CDR circuit -- sub‐harmonic frequency extraction scheme -- clock and data recovery circuit -- wide‐range frequency detection -- frequency locked loop -- FLL -- digital controlled oscillator -- frequency errors -- CDR loop tracking -- CMOS technology -- RMS jitter -- bit rate 8 Gbit/s to 10 Gbit/s -- size 40 nm -- power 29 mW -- voltage 1 V -- time 2.24 ps; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2018.6145
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Continuous‐rate all‐digital reference‐less clock and data recovery (CDR) circuit that utilises a sub‐harmonic extraction scheme for wide‐range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype reference‐less all‐digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8–10 Gbit/s PRBS 2 31 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.