8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction. Issue 20 (1st October 2018) - Yu, C.; Lee, D.; Park, H.; Jin, S.; Ahn, G.‐C.; Burm, J.
Abstract : Continuous‐rate all‐digital reference‐less clock and data recovery (CDR) circuit that utilises a sub‐harmonic extraction scheme for wide‐range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype reference‐less all‐digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8–10 Gbit/s PRBS 2 31 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.