2 ps resolution, fine‐grained delay element in 28 nm FDSOI. Issue 23 (1st November 2015)

• Record Type: Journal Article
• Authors: Hua, W.; Tadros, R.N.; Beerel, P.
• Is Part Of: Electronics letters. Volume 51:Issue 23(2015)
• Page Start: 1848
• Page End: 1850
• Publication Date: 2015-11-01
• Subjects: silicon‐on‐insulator -- leakage currents -- energy consumption; fine‐grained delay element -- FDSOI -- diversely body‐biased current‐starved delay element -- fine‐grained DE -- fully depleted silicon‐on‐insulator back‐body biasing -- delay quantisation error -- leakage current -- energy consumption -- size 28 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.2667
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel diversely body‐biased current‐starved delay element (DE) architecture for fine‐grained DEs is presented. Using fully depleted silicon‐on‐insulator back‐body biasing, it achieves a resolution of 2 ps with a delay quantisation error of 7.1%. Compared with the state‐of‐the‐art DEs, it exhibits the least leakage current and efficient overall energy consumption and is the most robust to process variations.