2 ps resolution, fine‐grained delay element in 28 nm FDSOI. Issue 23 (1st November 2015) - Hua, W.; Tadros, R.N.; Beerel, P.
Abstract : A novel diversely body‐biased current‐starved delay element (DE) architecture for fine‐grained DEs is presented. Using fully depleted silicon‐on‐insulator back‐body biasing, it achieves a resolution of 2 ps with a delay quantisation error of 7.1%. Compared with the state‐of‐the‐art DEs, it exhibits the least leakage current and efficient overall energy consumption and is the most robust to process variations.