SOI high‐voltage LDMOS with novel triple‐layer top silicon based on thin BOX. Issue 3 (1st January 2013)

• Record Type: Journal Article
• Authors: Hu, S.D.; Zhang, L.; Luo, J.; Tan, K.Z.; Chen, W.S.; Gan, P.; Zhou, X.C.; Zhu, Z.
• Is Part Of: Electronics letters. Volume 49:Issue 3(2013)
• Page Start: 223
• Page End: 225
• Publication Date: 2013-01-01
• Subjects: Si; size -- voltage; elemental semiconductors -- MIS devices -- silicon -- silicon‐on‐insulator; Si -- size 0.4 mum -- voltage 624 V -- triple‐layer top silicon -- high‐voltage blocking state -- n+ silicon -- p− silicon -- p‐top layer -- n− silicon -- TLTS LDMOS top silicon layer -- thin BOX -- novel triple‐layer top silicon -- SOI high‐voltage LDMOS; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2012.2988
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel SOI high‐voltage LDMOS with a triple‐layer top silicon (TLTS) is investigated. The top silicon layer of the TLTS LDMOS consists of n − silicon with a p‐top layer, p − silicon in the middle, and n + silicon on the interface. On the condition of high‐voltage blocking state, the electric fields of the drift region and BOX are modulated and optimised by the triple‐layer top silicon, respectively, which induces a high BV of 624 V for the TLTS LDMOS with a thin buried oxide layer (BOX) of 0.4 µm. Compared with several SOI devices, the proposed TLTS LDMOS has a higher figure‐of‐merit.