A latch-up-free LVTSCR with improved overshoot characteristic for ESD protection in 40 nm CMOS process. (26th May 2021)

• Record Type: Journal Article
• Authors: Chen, Rui-Bo; Liu, Hong-Xia; Guo, Dan; Huang, Wei; Huang, Xiao-Zong; Liu, Zhiwei
• Is Part Of: Semiconductor science and technology. Volume 36:Number 6(2021)
• Publication Date: 2021-05-26
• Subjects: electrostatic discharge (ESD) -- silicon-controlled rectifier (SCR) -- bipolar junction transistor (BJT) -- overshoot voltage; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/abf3a9
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: In this paper, a novel robust low-voltage-triggered silicon-controlled rectifier (LVTSCR) with high holding voltage, low trigger voltage, and low overshoot voltage has been proposed for 5 V integrated circuit electrostatic discharge (ESD) protection. The new LVTSCR integrates an extra low-resistance current path by embedding an NMOS transistor into the traditional LVTSCR. This extra current path will divert part of the ESD current, thus resulting in a lower overshoot voltage as well as better quasi-static I–V characteristics in the new structure. As such, the holding voltage of the new LVTSCR has been increased by ∼23%, the quasi-static triggering characteristic has been decreased by ∼8%, and the overshoot voltage has been improved by ∼38%.