Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits. (February 2021)

• Record Type: Journal Article
• Authors: Gupta, Neha; Shah, Ambika Prasad; Kumar, Rana Sagar; Raut, Gopal; Dhakad, Narendra Singh; Vishvakarma, Santosh Kumar
• Is Part Of: Microelectronics and reliability. Volume 117(2021)
• Publication Date: 2021-02
• Subjects: Bias temperature instability (BTI) -- Reliability -- Soft error rate (SER) -- Voltage bootstrapped circuit -- Stress time; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2020.114013
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced V th sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher. Highlights: An aging resilient NMOS only reliable voltage bootstrapped Schmitt trigger circuit (VB-ST) is proposed. Derive the expressions for the leakage current estimation of the proposed VB-ST circuit. Radiation tolerance methodology has been analyzed for the proposed VB-ST circuit. Threshold voltage sensitivity has been analyzed with temperature change. For the performance characterization, a novel figure of merit has been proposed.