(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era. (26th April 2017)

• Record Type: Journal Article
• Authors: Hoentschel, Jan; Carter, Rick; Rice, Bryan
• Is Part Of: ECS transactions. Volume 77:Number 5(2017)
• Page Start: 3
• Page End: 15
• Publication Date: 2017-04-26
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07705.0003ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : System- and process-level innovations based on VLSI-CMOS technologies are the drivers to continue Moore's Law. Especially in the last decade an ever-increasing component integration on SoC's has driven cost scaling and will continue to do so while approaching the IoT and wearable device area. To keep pace with the manufacturing cost per device scaling an acceleration of new processing methods, concepts and materials has been introduced, such as local strained Si, high-k metal gate, ultra-low-k, 3D FinFET and FDSOI devices. New integration techniques like double and quadruple patterning are needed since EUV lithography cannot be easy introduced in high volume manufacturing. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. SoC innovations need to focus on 3D multi-die package integrations on system level.