(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires. (26th April 2017)

• Record Type: Journal Article
• Authors: Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy Yakovitch; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Schram, Tom; Kunnen, Eddy; Ragnarsson, Lars-Åke; Dekkers, Harold F. W.; Hopf, Toby; Devriendt, Katia; Tsvetanova, Diana; Chew, Soon Aik; Kikuchi, Yoshiaki; Van Besien, Els; Rosseel, Erik; Mannaert, Geert; De Keersgieter, An; Chasin, Adrian; Kubicek, Stefan; Dangol, Anish; Demuynck, Steven; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto
• Is Part Of: ECS transactions. Volume 77:Number 5(2017)
• Page Start: 19
• Page End: 30
• Publication Date: 2017-04-26
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07705.0019ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We report on gate-all-around (GAA) N- and P-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to FinFET reference devices. Furthermore, CMOS integration of GAA MOSFETs is demonstrated. Threshold voltage tuning is achieved by nanowire-compatible dual-work-function metal integration.