(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities. (4th May 2016)

• Record Type: Journal Article
• Authors: Gaben, Loïc; Barraud, Sylvain; Samson, Marie-Pierre; Jaud, Marie-Anne; Martinie, Sébastien; Rozeau, Olivier; Lacord, Joris; Arvet, Christian; Vizioz, Christian; Bustos, Jessy; Dallery, Jacques-Alexandre; Pauliac, Sébastien; Balan, Viorel; Euvrard-Colnat, Catherine; Perrot, Cédric; Loup, Virginie; Besson, Pascal; Hartmann, Jean-Michel; Monfray, Stéphane; Boeuf, Frédéric; Skotnicki, Thomas; Balestra, Francis; Vinet, Maud
• Is Part Of: ECS transactions. Volume 72:Number 4(2016)
• Page Start: 43
• Page End: 54
• Publication Date: 2016-05-04
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07204.0043ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : Stacked-NW FETs pave the way for significant increase in device effective width over FinFET and FDSOI. An increase of performance and/or a decrease of device footprint is expected by using thin and wide NW channels also known as nanosheets or nanoplates. This paper points out Gate Last integration issues of stacked-NWs. Two solutions labeled as NW First and NW Last are presented featuring internal spacer formation. A demonstration of self-aligned gate and spacers is proposed, involving Hydrogen Silsesquioxane (HSQ) lithography through silicon channels.