(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities. (4th May 2016) - Gaben, Loïc; Barraud, Sylvain; Samson, Marie-Pierre; Jaud, Marie-Anne; Martinie, Sébastien; Rozeau, Olivier; Lacord, Joris; Arvet, Christian; Vizioz, Christian; Bustos, Jessy; Dallery, Jacques-Alexandre; Pauliac, Sébastien; et al.
Abstract : Stacked-NW FETs pave the way for significant increase in device effective width over FinFET and FDSOI. An increase of performance and/or a decrease of device footprint is expected by using thin and wide NW channels also known as nanosheets or nanoplates. This paper points out Gate Last integration issues of stacked-NWs. Two solutions labeled as NW First and NW Last are presented featuring internal spacer formation. A demonstration of self-aligned gate and spacers is proposed, involving Hydrogen Silsesquioxane (HSQ) lithography through silicon channels.