Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage. (23rd April 2019)

• Record Type: Journal Article
• Authors: Diaz Llorente, Carlos; G. Theodorou, Christoforos; Colinge, Jean-Pierre; Cristoloveanu, Sorin; Martinie, Sebastien; Le Royer, Cyrille; Ghibaudo, Gerard; Vinet, Maud
• Is Part Of: ECS transactions. Volume 89:Number 3(2019)
• Page Start: 111
• Page End: 120
• Publication Date: 2019-04-23
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08903.0111ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : A thorough investigation of trap density ( Dit ) at the interfaces of FD-SOI Tunnel FET (TFET) devices is presented. Charge pumping (CP) method confirms a larger average defect concentration at the top interface of Low-Temperature processed TFETs than in devices made using a standard high-temperature process. Back-gate bias is used to avoid probing the back-interface traps. We demonstrate the link between the CP current (experiments) and the carrier concentration (TCAD) at the interfaces during measurement. Simulation results demonstrate that the unusual variation of CP current in ultrathin FD-SOI depends on the carriers available for recombination at both front and back interfaces.