Reducing false positives due to double adjacent errors in instruction TLBs. (November 2019)

• Record Type: Journal Article
• Authors: Sánchez-Macián, A.; Aranda, L.A.; Reviriego, P.; Maestro, J.A.
• Is Part Of: Microelectronics and reliability. Volume 102(2019)
• Publication Date: 2019-11
• Subjects: Error detection -- Fault tolerance -- Reliability -- Translation lookaside buffer; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2019.113494
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Translation lookaside buffers (TLBs) are cache structures used to make the translation process between virtual pages and physical pages faster. Instruction TLBs store the virtual page number of the last accessed instruction memory pages and the corresponding physical page numbers. Single and double adjacent errors, which are common in harsh environments, may affect TLBs. This paper presents a technique to provide instruction TLB resilience to these single and double adjacent errors without additional storage requirements, by taking advantage of the spatial locality principle that is present in program execution. Highlights: Instruction TLB protected by taking advantage of the spatial locality principle. Increasing the intrinsic protection against false positives caused by single and double adjacent errors in the VPN. Adding a parity bit reduces false positives due to single, double-adjacent, triple and quadruple-adjacent errors. In this last case, it does not increase the delay when querying the iTLB.