AM3D: An accurate crosstalk probability modeling to predict channel delay in 3D ICs. (November 2019)

• Record Type: Journal Article
• Authors: Shirmohammadi, Zahra; Nikoofard, Amirhossein; Ershadi, Ghazal
• Is Part Of: Microelectronics and reliability. Volume 102(2019)
• Publication Date: 2019-11
• Subjects: Crosstalk fault modeling -- 3D ICs -- Through-Silicon-Vias (TSV) -- Time delay; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2019.06.071
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Migration from Two Dimensional Integrated Circuits (2D ICs) to Three Dimensional Integrated Circuits (3D ICs) reduces the delay due to the shorter wire length between sender and receiver. However, Through-Silicon-Vias (TSVs) that connect layers in the structure of 3D ICs can seriously increase the delay due to capacitance coupling between TSVs and lead to crosstalk fault. The severity of crosstalk faults depends on transitions appearing on TSVs that is called transition patterns. To propose an efficient crosstalk tackling mechanisms in 3D ICs, an accurate probability analytical model is required to predict the delay caused by TSVs (3D ICs) in the attendance of these transition patterns. In this regard, this paper proposes an accurate crosstalk probability model for 3D ICs called AM3D that estimates the latency of communication channels of 3D ICs in the attendance of crosstalk faults. The model is applicable for both non-protected TSVs and TSVs which are protected by crosstalk mitigation mechanisms. In order to accredit our proposed model, various SPICE simulations are conducted and obtained outcomes in different benchmarks are compared with extracted results from AM3D. Comparisons present an average of 1.81% discrepancies between the time delay obtained from SPICE simulations and time delay calculated by our proposed model.