Fabrication Variability in Multiple Gate MOSFETs: A Bulk FinFET Study. (5th January 2016)

• Record Type: Journal Article
• Authors: Chen, C.-Y.; Lin, J. T.; Chiang, M.-H.
• Is Part Of: ECS journal of solid state science and technology. Volume 5:Number 4(2016)
• Page Start: P3096
• Page End: P3100
• Publication Date: 2016-01-05
• Subjects: drain-induced barrier lowing -- FinFET -- interfacetraps -- line-edge-roughness -- random dopant fluctuation -- subthreshold -- subthreshold swing -- work function variation; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0181604jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : Process variations have brought challenges to continuous CMOS technology scaling. Among the variability issues, work function variation, line-edge-roughness and random dopant fluctuation are most of concern. Such variation issues are inevitable from devices fabrication and often result in intolerable threshold voltage variation. When the technology migrates from planar to nonplanar CMOS, process variations remain. However the impacts of variations on device characteristics are fundamentally different due to different physical aspect. In this paper, we present an experimental study on process variations in bulk FinFETs with a focus on subthreshold characteristics including drain-induced barrier lowing and subthreshold swing. Using the data measured from long and short channel devices in wide and narrow fins, we are able to differentiate the variation impacts from each of the device parameters. Our data suggest that the fin width variation is less of concern in long channel devices while the narrow fin width gives smaller mean DIBL values. However, the narrow fin with width less than channel length is required to avoid excessive variation impacts in addition to short-channel effects.