A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter. (December 2020)

• Record Type: Journal Article
• Authors: Wu, Jin; Chen, Shuang; Hu, Kang; Zheng, Lixia; Sun, Weifeng
• Is Part Of: Microelectronics journal. Volume 106(2020)
• Publication Date: 2020-12
• Subjects: Multiple delay locked loop -- Phase calibration -- SPOE -- TDC; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104926
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a low jitter multiplying delay-locked loop (MDLL) with static phase offset elimination (SPOE) applied to time-to-digital converter (TDC). To reduce static phase offset (SPO) between the reference clock and the output feedback clock, a SPOE techniques based on time amplifier (TA) is proposed, which the reference clock can be accurately injected for timing or phase calibration. The logic selector (LS) used a simplified form to complete mode switching with faster response times. The improved phase detector (PD) implements direct phase discrimination between the output feedback clock and the reference clock. The improved voltage-controlled delay line (VCDL) also makes the MDLL implementing a uniform split-phase output characteristic. The test chip is designed and fabricated in TSMC 0.35-μm 3.3 ​V complementary metal-oxide-semiconductor (CMOS) process which occupies a core area of 0.26 ​mm 2 . The measurement results show that the output clock jitters at 320 ​MHz frequency is 3.17 ps for root mean square, with the multiplication ratio of 8. The circuit has eight split-phase output clocks with a uniform separation within 45° ​± ​3.4°.