A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows. (November 2020)

• Record Type: Journal Article
• Authors: Pan, Xiangxin; Zhou, Xiong; Chang, Sheng; Ding, Zhaoming; Li, Qiang
• Is Part Of: Journal of semiconductors. Volume 41:Number 11(2020)
• Publication Date: 2020-11
• Subjects: adaptive bypass window -- number of oscillation cycles (NOC) -- offset -- split-and-recombination redundancy -- SAR ADC -- VCO-based comparator; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/41/11/112401
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: This paper proposes a technique that uses the number of oscillation cycles (NOC) of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The analysis of the number of bit cycles, power and static performance shows that three adaptive bypass windows reduce power consumption, and decrease DNL and have similar INL, compared with the SAR ADC without bypass windows. In addition, a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window. This design is implemented in 40 nm CMOS technology. The conversion frequency of the ADC reaches up to 30 MS/s. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input, consuming 380 μ W, down from 427 μ W without multiple adaptive bypass windows, at a 1.1 V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.