Investigation of electrical characteristics of flexible CMOS devices fabricated with thickness-controlled spalling process. (November 2020)

• Record Type: Journal Article
• Authors: Park, Honghwi; Lim, Changhee; Noh, Yeho; Lee, Chang-Ju; Won, Heungsup; Jung, Jaedong; Choi, Muhan; Kim, Jae-Joon; Yoo, Hocheon; Park, Hongsik
• Is Part Of: Solid-state electronics. Volume 173(2020)
• Publication Date: 2020-11
• Subjects: Thickness-controlled layer separation -- Spalling technique -- flexible CMOS devices -- Residual stress -- CMOS performance -- Separated layer thickness; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2020.107901
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Flexible Si CMOS devices are fabricated with thickness-controlled spalling process. Electrical characteristics of flexible CMOS devices are evaluated under various stress conditions. Excessive stress can cause the malfunction of flexible CMOS devices. Stress remaining in the layer after the spalling process is a major factor degrading the CMOS performance. Stresses are significantly dependent on the thickness of the separated device layers. Abstract: Processing techniques for the thickness-controlled layer separation of a single-crystalline semiconductor have been actively developed for manufacturing complementary metal–oxide–semiconductor (CMOS)-technology-based flexible devices. A mechanical separation process for thin semiconductor layers, called the spalling technique, has recently attracted much attention because of its process simplicity, thickness controllability, and kerf-less layer separation. In this paper, we show that the thickness of separated device layers and the residual stress in the layers are critical factors to determine the performance of flexible CMOS devices fabricated with the spalling process. We investigated the electrical characteristics of flexible field-effect transistors (FETs) and CMOS inverters under various stress conditions. The results show that the excessive stress induced in the device layers can cause a severe performance mismatch between n- and p-channel FETs that results in the malfunction of flexible silicon CMOS devices. In addition, we verified that the unrelaxed stress remaining in the device layer after the spalling/transfer process is a major factor degrading the CMOS performance. The results also show that the residual stress induced by the spalling/transfer process as well as the external stress by mechanical bending are significantly dependent on the thickness of the separated device layers.