Effects of solder degradation on the die temperature measurement via internal gate resistance. (November 2020)

• Record Type: Journal Article
• Authors: Kawahara, C.; Brandelero, J.; Pichon, P.; Mollov, S.
• Is Part Of: Microelectronics and reliability. Volume 114(2020)
• Publication Date: 2020-11
• Subjects: Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2020.113879
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The virtual junction temperature measurement via internal gate resistance ( T vg ) is attractive for the health monitoring of power modules. Using the gate resistance as Temperature Sensitive Electrical parameter (TSEP) permits precise and timely absolute temperature on the die where the gate is located. This paper investigates how this measurement relates to other parts of the power die, inclusive of aging effects such as die attach degradation. Using in-situ measurements and FEM simulations, a method for compensating the gate pad temperature error is proposed.