Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate. (October 2020)

• Record Type: Journal Article
• Authors: Chiang, Te-kuang
• Is Part Of: Microelectronics journal. Volume 104(2020)
• Publication Date: 2020-10
• Subjects: Quasi-3D potential approach -- Quasi-3D scaling theory -- Equivalent flat-band shift -- Subthreshold current -- Subthreshold logic gate -- Scaling factor -- Noise margin.; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104893
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band shift, a new subthreshold current model caused by the interface-trapped-charge is developed for the nanosheet FET. With the subthreshold current Isub, the noise margin (NM) of the subthreshold logic gate composed of nanosheet FET is thoroughly evaluated. It is found that the positive interface-trapped-charge can degrade the high noise margin (NMH ) due to its increased/decreased subthreshold current of N-FET/P-FET. On the contrary, the negative interface-trapped-charge can decrease/increase subthreshold current of N-FET/P-FET, which hence deteriorates the low noise margin (NML ). Both degradation of the subthreshold current and NM (i.e., ΔIsub and ΔNM) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor αmin that allows for the minimum noise margin degradation (ΔNM), the minimum channel length Lmin for the nanosheet FET can be obtained as it is readily applied for the subthreshold logic gate.