A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer. (December 2016)

• Record Type: Journal Article
• Authors: Liaw, Yue-Gie; Liao, Wen-Shiang; Wang, Mu-Chun; Lin, Cheng-Li; Zhou, Bin; Gu, Haoshuang; Li, Deshi; Zou, Xuecheng
• Is Part Of: Solid-state electronics. Volume 126(2016)
• Page Start: 46
• Page End: 50
• Publication Date: 2016-12
• Subjects: SOI -- FinFET -- Threshold voltage -- Drive current -- Off currents -- Subthreshold swing -- DIBL -- Transistor gate delay -- TCAD simulation -- Fully silicidation; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2016.09.017
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: The electrical performance of Si-based n-channel FinFETs as W/L/H = 21/30/83 nm with SiON gate dielectric was measured. The electrical characteristics of Si-based p-channel FinFETs as W/L/H = 21/30/83 nm with SiON gate dielectric were extracted. The top-view profile of Si multiple fins device with SEM photograph was exhibited. The electrical performance in TCAD simulation with and without work function adjustment was demonstrated. The cross-sectional profile of single FinFET with TEM image was demonstrated as Wfin = 8.6–11.4 nm and Hfin = 82.9 nm. Abstract: Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (ION ), off current (IOFF ), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (Lg ) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (Vth ) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically.