Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine. (9th October 2020)

• Record Type: Journal Article
• Authors: Shim, Wonbo; Seo, Jae-sun; Yu, Shimeng
• Is Part Of: Semiconductor science and technology. Volume 35:Number 11(2020)
• Publication Date: 2020-10-09
• Subjects: multilevel resistive random access memory -- write-verify -- read noise -- compute-in-memory -- deep learning inference engine; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/abb842
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: Accurate cell conductance tuning is critical to realizing multilevel resistive random access memory (RRAM)-based compute-in-memory inference engines. To tighten the distribution of the cells of each state, we developed a two-step write–verify scheme within a limited number of iterations, which was tested on a test vehicle based on HfO2 RRAM array to realize 2 bits per cell. The conductance of the cells is gathered in the targeted range within 10 loops of set and reset processes for each step. Moreover, the read noise of the RRAM cells is statistically measured and its impact on the upper bound of analog-to-digital converter (ADC) resolution is predicted. The result shows that the intermediate state cells under relatively high read voltage (e.g. 0.2 V) are vulnerable to the read noise. Fortunately, the aggregated read noise along the column will not disturb the output of a 5 bit ADC that is required for a 128 × 128 array with 2 bits per cell.