Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET. (9th September 2020)

• Record Type: Journal Article
• Authors: Tripathy, Manas Ranjan; Singh, Ashish Kumar; Samad, A; Singh, Prince Kumar; Baral, Kamalaksha; Jit, Satyabrata
• Is Part Of: Semiconductor science and technology. Volume 35:Number 10(2020)
• Publication Date: 2020-09-09
• Subjects: tunnel field effect transistor -- heterojunction -- subthreshold swing -- source pocket -- heterogeneous gate dielectric -- current mirror; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/aba418
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors (Ge/Si SPE-V-HTFETs) with and without a heterogeneous gate dielectric (HGD) structure for the first time. The DC performance parameters in terms of ION /IOFF and subthreshold swing (SS) are investigated for the proposed V-HTFETs. The average SS for the proposed V-HTFET with an HGD is found to be as low as 20 mV dec −1 compared to V-HTFET without any HGD (26 mV dec −1 ) at VDS = 0.5 V. The proposed Ge/Si SPE-V-HTFET with an HGD possesses higher cut-off frequency of 502 GHz and maximum frequency of oscillation of 2.33 THz at VDS = 0.5 V over the Ge/Si SPE-V-HTFET without any HGD which possesses cut-off frequency of 273 GHz and maximum frequency of oscillation of 1.47 THz. The proposed Ge/Si SPE-V-HTFET with and without an HGD have then been used for designing a basic current mirror circuit. Device-level study has been carried out using SILVACO ATLAS TM TCAD simulator while the circuit-level investigation has been performed using the look up table based Verilog-A models in the CADENCE Virtuoso tool. The performances of the Ge/Si SPE-V-HTFET with HGD based current mirror circuit is observed to be better than the corresponding current mirror circuit designed by Ge/Si SPE-V-HTFET without any HGD.