Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes. (4th December 2019)

• Record Type: Journal Article
• Authors: Dey, S; Jena, J; Mohapatra, E; Dash, T P; Das, S; Maiti, C K
• Is Part Of: Physica scripta. Volume 95:Number 1(2020)
• Publication Date: 2019-12-04
• Subjects: vertically-stacked nanowire FETs -- quantum confinement -- technology computer aided design (TCAD) -- density-gradient (DG) model -- metal grain granularity (MGG); Physics -- Periodicals; 530.05
• DOI: 10.1088/1402-4896/ab4621
• Languages: English
• ISSNs: 0031-8949

Abstract

Abstract: Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.