Characterization and electrical modeling of polycrystalline silicon vertical thin film transistors. (September 2020)
- Record Type:
- Journal Article
- Title:
- Characterization and electrical modeling of polycrystalline silicon vertical thin film transistors. (September 2020)
- Main Title:
- Characterization and electrical modeling of polycrystalline silicon vertical thin film transistors
- Authors:
- Zhang, Peng
Jacques, Emmanuel
Rogel, Régis
Pichon, Laurent
Bonnaud, Olivier - Abstract:
- Highlights: The rough interface of the active layer and the rugged sidewall adversely affects the electrical characteristics of vertical TFTs. The vertical TFT with Si3 N4 barrier layer shows same threshold voltage and subthreshold slope, however, a larger transconductance and field effect mobility in comparison to the vertical TFT with SiO2 barrier layer. The electrical parameters of the vertical TFTs and lateral TFT are analyzed by density of states (DOS) using Suzuki method, subthreshold slope method, and Grünewald method. Abstract: Thin film transistors (TFTs) with lateral channels are limited in current density due to the design rule. For many applications with improved integration, the introduction of vertical channels reduces channel lengths while increasing current density per unit surface area. In previous works, vertical TFTs have been designed and manufactured using low-temperature polycrystalline silicon technology (T ≤ 600 °C), with a solid phase crystallization (SPC) based process. In this case, the introduction of an insulating layer between source and drain films has resulted in a significant improvement in the electrical characteristics, mainly in the On/Off state current (Ion /Ioff ) ratio. However, the active layer is deposited on the sidewalls obtained by plasma etching, and the etching process results in morphological defects on the sidewalls that adversely affect the electrical characteristics. The purpose of this paper is to understand the origin andHighlights: The rough interface of the active layer and the rugged sidewall adversely affects the electrical characteristics of vertical TFTs. The vertical TFT with Si3 N4 barrier layer shows same threshold voltage and subthreshold slope, however, a larger transconductance and field effect mobility in comparison to the vertical TFT with SiO2 barrier layer. The electrical parameters of the vertical TFTs and lateral TFT are analyzed by density of states (DOS) using Suzuki method, subthreshold slope method, and Grünewald method. Abstract: Thin film transistors (TFTs) with lateral channels are limited in current density due to the design rule. For many applications with improved integration, the introduction of vertical channels reduces channel lengths while increasing current density per unit surface area. In previous works, vertical TFTs have been designed and manufactured using low-temperature polycrystalline silicon technology (T ≤ 600 °C), with a solid phase crystallization (SPC) based process. In this case, the introduction of an insulating layer between source and drain films has resulted in a significant improvement in the electrical characteristics, mainly in the On/Off state current (Ion /Ioff ) ratio. However, the active layer is deposited on the sidewalls obtained by plasma etching, and the etching process results in morphological defects on the sidewalls that adversely affect the electrical characteristics. The purpose of this paper is to understand the origin and effects of these defects using different models. Thus, the transfer characteristics are analyzed in detail, with Suzuki method to calculate the density of states, while subthreshold slope method and Grünewald method are adopted to verify the Suzuki method for the deep and shallow trap densities, respectively. These methods provide an approach for DOS calculation independent of temperature-related measurement. … (more)
- Is Part Of:
- Solid-state electronics. Volume 171(2020)
- Journal:
- Solid-state electronics
- Issue:
- Volume 171(2020)
- Issue Display:
- Volume 171, Issue 2020 (2020)
- Year:
- 2020
- Volume:
- 171
- Issue:
- 2020
- Issue Sort Value:
- 2020-0171-2020-0000
- Page Start:
- Page End:
- Publication Date:
- 2020-09
- Subjects:
- Vertical thin film transistors -- Low temperature polycrystalline silicon -- Density of states -- Conduction modeling
Semiconductors -- Periodicals
Semiconducteurs -- Périodiques
621.38152 - Journal URLs:
- http://www.sciencedirect.com/science/journal/00381101 ↗
http://www.elsevier.com/journals ↗ - DOI:
- 10.1016/j.sse.2020.107798 ↗
- Languages:
- English
- ISSNs:
- 0038-1101
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 8327.385000
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 14006.xml