On-line self-test mechanism for Dual-Core Lockstep System-on-Chips. (September 2020)

• Record Type: Journal Article
• Authors: Floridia, Andrea; Sanchez, Ernesto
• Is Part Of: Microelectronics and reliability. Volume 112(2020)
• Publication Date: 2020-09
• Subjects: Multi-core systems -- On-line testing -- Self-test -- Safety-critical applications -- Software-based self-test -- Functional safety -- Lockstep computing; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2020.113770
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The Dual-Core Lockstep configuration is largely employed in safety-critical System-on-Chips for the sake of compliance with functional safety standards. Such configuration includes two processor cores paired together, always fed with the same identical inputs and their outputs are continuously compared by a set of comparators. However, permanent faults affecting the comparators may invalidate the system functionalities, thus in-field self-test mechanisms are mandatory. In this paper, different in-field self-test solutions are first discussed. Then, a hybrid hardware-software scheme for the on-line testing of the lockstep logic is proposed. Such a solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor. Exhaustive experiments demonstrated that it is possible to achieve a fault coverage of stuck-at faults greater than 99%, while at the same time significantly reduce the area overhead of classical approaches.