Influence of CMP damage induced during flattening SiC epitaxial layer on device performances. (September 2020)

• Record Type: Journal Article
• Authors: Masumoto, Keiko; Senzaki, Junji; Hasegawa, Masaki; Ohira, Kentaro; Kojima, Kazutoshi; Kobayashi, Kenji; Okumura, Hajime
• Is Part Of: Materials science in semiconductor processing. Volume 116(2020)
• Publication Date: 2020-09
• Subjects: Silicon carbide -- Epitaxial layer -- Chemical mechanical polishing -- Mirror electron inspection system -- Dislocation half-loop; Semiconductors -- Periodicals; Integrated circuits -- Materials -- Periodicals; Semiconducteurs -- Périodiques; Circuits intégrés -- Matériaux -- Périodiques; Electronic journals; 621.38152
• DOI: 10.1016/j.mssp.2020.105162
• Languages: English
• ISSNs: 1369-8001

Abstract

Abstract: Thick silicon carbide (SiC) epitaxial layers, which are required for the fabrication of SiC ultra-high voltage devices, have to be flattened by chemical mechanical polishing (CMP) in order to eliminate bunched-step segments, shallow pits, and epi-crowns. However, the negative effects of CMP on device performance is concerning. In this research, we attempted to evaluate a SiC epitaxial layer surface after flattening by CMP and to clarify the extent of CMP damage on the performance of a 4 H –SiC PiN diode. As a result, a bundle of dislocation half-loops, which were detected by a mirror electron microscope (MEM) inspection system (Hitachi High-Technologies Mirelis VM-1000), was found to occur beneath the epitaxial layer surface flattened by CMP and led to current leakage of the PiN diode.