New DG FeFET topology with enhanced SS and non-hysteretic behavior. (June 2020)

• Record Type: Journal Article
• Authors: Gnani, E.; Malagò, P.; Gnudi, A.; Reggiani, S.
• Is Part Of: Solid-state electronics. Volume 168(2020)
• Publication Date: 2020-06
• Subjects: Ferroelectric FET -- Subthreshold slope -- Low-power electronics -- Ferroelectric polarization -- Nanoscale transistor -- Quantum confinement; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.107727
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 mV/dec with a hysteresis-free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The floating gate can be extended above the source and drain regions, so that its capacitance can be suitably optimized to ensure device stability. We found that both the overlap capacitance and quantum confinement are beneficial for the amplification factor. The I ON improvement over the standard DG MOSFET turns out to be 23.7×, with no degradation of the intrinsic transit time.