Novel fine-grain back-bias assist techniques for 3D-monolithic 14 nm FDSOI top-tier SRAMs. (June 2020)

• Record Type: Journal Article
• Authors: Bosch, D.; Garros, X.; Makosiej, A.; Ciampolini, L.; Weber, O.; Lacord, J.; Cluzel, J.; Giraud, B.; Berthelon, R.; Cibrario, G.; Brunet, L.; Batude, P.; Fenouillet-Béranger, C.; Lattard, D.; Colinge, J.P.; Balestra, F.; Andrieu, F.
• Is Part Of: Solid-state electronics. Volume 168(2020)
• Publication Date: 2020-06
• Subjects: 3D monolithic -- FDSOI -- BTI stress -- Supply Read Retention Voltage (SRRV) -- SRAM margins -- SNM -- WNM -- Variability -- Body biasing -- SPICE -- Technology-design optimization; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.107720
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm 2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage Vmin by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs.