Inter-tier electrostatic coupling effects in 3D sequential integration devices and circuits. (June 2020)

• Record Type: Journal Article
• Authors: Sideris, P.; Brunet, L.; Ciampolini, L.; Sicard, G.; Batude, P.; Theodorou, C.
• Is Part Of: Solid-state electronics. Volume 168(2020)
• Publication Date: 2020-06
• Subjects: SOI -- CMOS -- Fully depleted -- S3D -- Monolithic 3D -- 3D sequential integration -- Stacked -- Coupling -- SRAM cells -- Static random access memory -- RSNM -- WSNM -- SRRV -- Circuit stability; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.107715
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.