Low On‐Resistance and Low Trapping Effects in 1200 V Superlattice GaN‐on‐Silicon Heterostructures. Issue 7 (11th November 2019)

• Record Type: Journal Article
• Authors: Kabouche, Riad; Abid, Idriss; Püsche, Roland; Derluyn, Joff; Degroote, Stefan; Germain, Marianne; Tajalli, Alaleh; Meneghini, Matteo; Meneghesso, Gaudenzio; Medjdoub, Farid
• Other Names: Shahedipour-Sandvik F. Shadi guestEditor.; Qhalid Fareed guestEditor.
• Is Part Of: Physica status solidi. Volume 217:Issue 7(2020)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-11-11
• Subjects: GaN -- low on-resistance -- low trapping effects -- silicon -- superlattices; Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.201900687
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : Herein, the development of gallium nitride on silicon (GaN‐on‐Si) heterostructures targeting 1200 V power applications is reported. In particular, it is shown that the insertion of superlattices (SLs) into the buffer layers allows pushing the vertical breakdown voltage above 1200 V without generating additional trapping effects as compared with a more standard optimized step‐graded AlGaN‐based epistructure using a similar total buffer thickness. DC characterizations of fabricated transistors by means of back‐gating measurements reflect both the enhancement of the breakdown voltage and the low trapping effects up to 1200 V. These results show that a proper buffer optimization and the insertion of SL pave the way to GaN‐on‐Si lateral power transistors operating at 1200 V with low on‐resistance and low trapping effects. Abstract : DC and back‐gating characterizations are performed on superlattice (SL)‐based gallium nitride on silicon (GaN‐on‐Si) heterostructures. These results show that a proper buffer optimization and the insertion of SL pave the way to GaN‐on‐Si lateral power transistors operating at 1200 V with low on‐resistance and low trapping effects.