Cite
HARVARD Citation
Poovendran, R. et al. (2019). An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design. Concurrency and computation. p. n/a. [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Poovendran, R. et al. (2019). An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design. Concurrency and computation. p. n/a. [Online].