An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design. (10th August 2018)

• Record Type: Journal Article
• Authors: Poovendran, R.; Sumathi, S.
• Other Names: Karthikeyan M. guestEditor.; Chilamkurti Naveen guestEditor.; Li Xiong guestEditor.
• Is Part Of: Concurrency and computation. Volume 31:Number 14(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-08-10
• Subjects: application specified integrated chip -- diametrical mesh -- field programmable gate array -- network‐on‐chip -- 4x4‐Router Architecture–Carry Select Adder; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.4760
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: The incorporation of network‐on‐Chip with communication delivers a strengthening solution to the rising complexity and problems in system‐on‐chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4‐Router Architecture–Carry Select Adder (4x4‐RA‐CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.